`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:32:21 11/13/2011 
// Design Name: 
// Module Name:    exerciser 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module exerciser_module(
  input           CLK,
  input           RST,

  input   [31:0]  S_AWADDR,
  input           S_AWVALID,
  output          S_AWREADY,
  input   [31:0]  S_WDATA,
  input   [3:0]   S_WSTRB,
  input           S_WVALID,
  output          S_WREADY,
  output  [1:0]   S_BRESP,
  output          S_BVALID,
  input           S_BREADY,
  input   [31:0]  S_ARADDR,
  input           S_ARVALID,
  output          S_ARREADY,
  output  [31:0]  S_RDATA,
  output  [1:0]   S_RRESP,
  output          S_RVALID,
  input           S_RREADY,

  input           S_TVALID,
  output          S_TREADY,
  input   [127:0] S_TDATA,
  input   [3:0]   S_TSTRB,
  input   [47:0]  S_TUSER,
  input           S_TLAST,

  output          M_TVALID,
  input           M_TREADY,
  output  [127:0] M_TDATA,
  output  [3:0]   M_TSTRB,
  output  [47:0]  M_TUSER,
  output          M_TLAST,

  output  [0:0]   M0_AWID,
  output  [31:0]  M0_AWADDR,
  output  [7:0]   M0_AWLEN,
  output  [2:0]   M0_AWSIZE,
  output  [1:0]   M0_AWBURST,
  output          M0_AWVALID,
  input           M0_AWREADY,
  output  [127:0] M0_WDATA,
  output  [15:0]  M0_WSTRB,
  output          M0_WLAST,
  output          M0_WVALID,
  input           M0_WREADY,
  input   [0:0]   M0_BID,
  input   [1:0]   M0_BRESP,
  input           M0_BVALID,
  output          M0_BREADY,
  output  [0:0]   M0_ARID,
  output  [31:0]  M0_ARADDR,
  output  [7:0]   M0_ARLEN,
  output  [2:0]   M0_ARSIZE,
  output  [1:0]   M0_ARBURST,
  output          M0_ARVALID,
  input           M0_ARREADY,
  input   [0:0]   M0_RID,
  input   [127:0] M0_RDATA,
  input   [1:0]   M0_RRESP,
  input           M0_RLAST,
  input           M0_RVALID,
  output          M0_RREADY
  );

  wire rp_en;
  wire [3:0] rp_we;
  wire [5:0] rp_a;
  wire [31:0] rp_rd;
  wire [31:0] rp_wd;
  wire rp_rdy;
  
  AxiLite2RP 
  al2rp(
    .CLK(CLK),
    .RST(RST),
    
    .S_AWADDR   (S_AWADDR ),
    .S_AWVALID  (S_AWVALID),
    .S_AWREADY  (S_AWREADY),
    .S_WDATA    (S_WDATA  ),
    .S_WSTRB    (S_WSTRB  ),
    .S_WVALID   (S_WVALID ),
    .S_WREADY   (S_WREADY ),
    .S_BRESP    (S_BRESP  ),
    .S_BVALID   (S_BVALID ),
    .S_BREADY   (S_BREADY ),
    .S_ARADDR   (S_ARADDR ),
    .S_ARVALID  (S_ARVALID),
    .S_ARREADY  (S_ARREADY),
    .S_RDATA    (S_RDATA  ),
    .S_RRESP    (S_RRESP  ),
    .S_RVALID   (S_RVALID ),
    .S_RREADY   (S_RREADY ),
    
    .RP_EN      (rp_en ),
    .RP_WE      (rp_we ),
    .RP_A       (rp_a  ),
    .RP_RD      (rp_rd ),
    .RP_WD      (rp_wd ),
    .RP_RDY     (rp_rdy)
  );

  wire        r_en = (rp_a[5:3] == 3'b000) ? rp_en : 1'b0;
  wire [3:0]  r_we = (rp_a[5:3] == 3'b000) ? rp_we : 4'b0;
  wire [2:0]  r_a = rp_a[2:0];
  wire [31:0] r_wd = rp_wd;
  wire [31:0] r_rd;
  wire        r_rdy;
  
  wire        p_en = (rp_a[5:3] == 3'b001) ? rp_en : 1'b0;
  wire [3:0]  p_we = (rp_a[5:3] == 3'b001) ? rp_we : 4'b0;
  wire [2:0]  p_a = rp_a[2:0];
  wire [31:0] p_wd = rp_wd;
  wire [31:0] p_rd;
  wire        p_rdy;
  
  assign rp_rd =  (rp_a[5:3] == 3'b000) ? r_rd :
                  (rp_a[5:3] == 3'b001) ? p_rd : 32'b0;
  assign rp_rdy = r_rdy || p_rdy;
  
  axis_player 
  transmitter(
    .CLK          (CLK),
    .RST          (RST),

    .RP_EN        (p_en),
    .RP_WE        (p_we),
    .RP_A         (p_a),
    .RP_DI        (p_wd),
    .RP_DO        (p_rd),
    .RP_RDY       (p_rdy),
    
    .M_TVALID     (M_TVALID),
    .M_TREADY     (M_TREADY),
    .M_TDATA      (M_TDATA),
    .M_TSTRB      (M_TSTRB),
    .M_TUSER      (M_TUSER),
    .M_TLAST      (M_TLAST),

    .M_ARID       (M0_ARID),
    .M_ARADDR     (M0_ARADDR),
    .M_ARLEN      (M0_ARLEN),
    .M_ARSIZE     (M0_ARSIZE),
    .M_ARBURST    (M0_ARBURST),
    .M_ARVALID    (M0_ARVALID),
    .M_ARREADY    (M0_ARREADY),
    .M_RID        (M0_RID),
    .M_RDATA      (M0_RDATA),
    .M_RRESP      (M0_RRESP),
    .M_RLAST      (M0_RLAST),
    .M_RVALID     (M0_RVALID),
    .M_RREADY     (M0_RREADY));
  
  axis_recorder
  receiver(
    .CLK          (CLK),
    .RST          (RST),

    .RP_EN        (r_en),
    .RP_WE        (r_we),
    .RP_A         (r_a),
    .RP_DI        (r_wd),
    .RP_DO        (r_rd),
    .RP_RDY       (r_rdy),

    .S_TVALID     (S_TVALID),
    .S_TREADY     (S_TREADY),
    .S_TDATA      (S_TDATA),
    .S_TSTRB      (S_TSTRB),
    .S_TUSER      (S_TUSER),
    .S_TLAST      (S_TLAST),
  
    .M_AWID       (M0_AWID      ),
    .M_AWADDR     (M0_AWADDR    ),
    .M_AWLEN      (M0_AWLEN     ),
    .M_AWSIZE     (M0_AWSIZE    ),
    .M_AWBURST    (M0_AWBURST   ),
    .M_AWVALID    (M0_AWVALID   ),
    .M_AWREADY    (M0_AWREADY   ),
    .M_WDATA      (M0_WDATA     ),
    .M_WSTRB      (M0_WSTRB     ),
    .M_WLAST      (M0_WLAST     ),
    .M_WVALID     (M0_WVALID    ),
    .M_WREADY     (M0_WREADY    ),
    .M_BID        (M0_BID       ),
    .M_BRESP      (M0_BRESP     ),
    .M_BVALID     (M0_BVALID    ),
    .M_BREADY     (M0_BREADY    ));

endmodule
